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INTEGRATED CIRCUITS
DATA SHEET
TDA9952 10-bit, 3.0 V, 25 Msps analog-to-digital interface for CCD cameras
Preliminary specification Supersedes data of 2001 Jul 04 2002 Aug 21
Philips Semiconductors
Preliminary specification
10-bit, 3.0 V, 25 Msps analog-to-digital interface for CCD cameras
FEATURES * Sample rate = 25 Msps;10-bit resolution * Single 3.0 V supply operation (2.2 to 3.6 V operation for the digital outputs) * Low power consumption: only 115 mW at 2.7 V * Power consumption in standby mode: 4.5 mW (typical value) * Programmable gain amplifier: gain range = 36 dB in 0.1 dB steps * Correlated double sampling * Internal input buffer for the correlated double sampling * Fully programmable via a 3-wire serial interface * 8-bit DAC included for external analog settings * TTL-compatible inputs and CMOS-compatible outputs. APPLICATIONS * Video camcorders * Digital still cameras * PC-cameras. ORDERING INFORMATION PACKAGES TYPE NUMBER NAME TDA9952HL TDA9952HN LQFP48 HVQFN48 DESCRIPTION plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm plastic, heatsink very thin quad flat package; no leads; 48 terminals; body 7 x 7 x 0.85 mm GENERAL DESCRIPTION
TDA9952
The TDA9952 is a 10-bit analog-to-digital interface for CCD cameras. The device consists of a Correlated Double Sampling (CDS) circuit, a digitally Programmable Gain Amplifier (PGA), a black level clamp and a 10-bit Analog-to-Digital Converter (ADC). An internal CDS input buffer is incorporated in order to avoid using an external buffer that would consume more power and therefore optimizing the application for low noise, low power working. The PGA gain, the ADC clamp level and other settings are controlled via a 3-wire serial digital interface. An additional DAC is provided for system controls. The TDA9952 operates from a single 3 V power supply (2.7 V minimum) and dissipates 135 mW (typical value).
VERSION SOT313-2 SOT619-1
2002 Aug 21
2
Philips Semiconductors
Preliminary specification
10-bit, 3.0 V, 25 Msps analog-to-digital interface for CCD cameras
QUICK REFERENCE DATA SYMBOL VCCA VCCD VCCO ICCA ICCD ICCO ADCres Vi(CDS)(p-p) fpix(max) fpix(min) DRPGA Ntot(rms) Ein(rms) Ptot PARAMETER analog supply voltage digital supply voltage digital outputs supply voltage analog supply current digital supply current digital outputs supply current ADC resolution maximum CDS input voltage (peak-to-peak value) maximum pixel rate minimum pixel rate PGA dynamic range total noise from CDS input to ADC output (RMS value) equivalent input noise voltage (RMS value) total power consumption PGA code = 00; see Fig.8 PGA code = 383 VCCA = VCCD = 3 V; VCCO = 2.5 V VCCA = VCCD = 2.7 V; VCCO = 2.2 V standby mode OCCD(max) = 100 mV OCCD(max) = 200 mV VCC = 2.85 V VCC 3.0 V all clamps active fpix = 25 MHz CONDITIONS MIN. 2.7 2.7 2.2 - - TYP. 3.0 3.0 2.5 43 2.0 0.5 10 - - - - - 36 0.4 145 135 115 4.5
TDA9952
MAX. 3.6 3.6 3.6 - - - - - - - 1 2 - - - - - -
UNIT V V V mA mA mA bits mV mV MHz MHz MHz dB LSB V mW mW mW
fpix = 25 MHz; CL = 10 pF; - input ramp response time is 800 s - 650 800 25 - - - - - - - -
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SHP 45 SHD 46 VCCA1 1 AGND1 2 VCCA6 41 AGND6 CLPOB CLPDM 40 44 48 BLK CLK OE 43 47 39 22 21 CDS CLOCK GENERATOR 37 38 DGND1 VCCD1 OGND2 VCCO2 CPCDS1 CPCDS2 VCCA2 AGND2 IN 8
BLOCK DIAGRAM
Philips Semiconductors
10-bit, 3.0 V, 25 Msps analog-to-digital interface for CCD cameras
TDA9952
CLAMP 9 7 3 4 CORRELATED DOUBLE SAMPLING PGA SHIFT
BLACK LEVEL SHIFT
36 35
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
input buffer
34 33 DATA FLIPFLOP 32 OUTPUT BUFFER 31 30 29 28 27
BLANKING 10-bit ADC
Fig.1 Block diagram.
handbook, full pagewidth
4
n.c. 25, 26 CLAMP VCCA3 AGND3 14 5 OFD DAC OFDOUT 11 12 6 TEST AGND4
Vref 9-BIT REGISTER 6-BIT REGISTER 24 23 8-BIT REGISTER INIT-ONPOWER SERIAL INTERFACE 10 OGND1 VCCO1 DCLPC
REGULATOR 20 42
13
15
16
19
18
17
FCE629
Preliminary specification
AGND5
VCCA4
VCCA5
SEN
SCLK SDATA VSYNC
STDBY
TDA9952
Philips Semiconductors
Preliminary specification
10-bit, 3.0 V, 25 Msps analog-to-digital interface for CCD cameras
PINNING SYMBOL VCCA1 AGND1 AGND2 IN AGND3 AGND4 VCCA2 CPCDS1 CPCDS2 DCLPC OFDOUT TEST AGND5 VCCA3 VCCA4 VCCA5 SDATA SCLK SEN VSYNC VCCD1 DGND1 VCCO1 OGND1 n.c. n.c. D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 OGND2 VCCO2 OE AGND6 2002 Aug 21 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 analog supply voltage1 analog ground 1 analog ground 2 input signal from CCD analog ground 3 analog ground 4 analog supply voltage 2 clamp storage capacitor pin 1 clamp storage capacitor pin 2 regulator decoupling pin analog output of the additional 8-bit control DAC test mode input pin (should be connected to AGND5) analog ground 5 analog supply voltage 3 analog supply voltage 4 analog supply voltage 5 serial data input for serial interface control serial clock input for serial interface strobe pin for serial interface vertical sync pulse input digital supply voltage 1 digital ground 1 digital output supply voltage 1 digital output ground 1 not connected not connected ADC digital output 0 (LSB) ADC digital output 1 ADC digital output 2 ADC digital output 3 ADC digital output 4 ADC digital output 5 ADC digital output 6 ADC digital output 7 ADC digital output 8 ADC digital output 9 (MSB) digital output ground 2 digital output supply voltage 2 DESCRIPTION
TDA9952
output enable control input (LOW: outputs active; HIGH: outputs in high-impedance) analog ground 6 5
Philips Semiconductors
Preliminary specification
10-bit, 3.0 V, 25 Msps analog-to-digital interface for CCD cameras
SYMBOL VCCA6 STDBY BLK CLPOB SHP SHD CLK CLPDM PIN 41 42 43 44 45 46 47 48 analog supply voltage 6 DESCRIPTION
TDA9952
standby mode control input (LOW: TDA9952 active; HIGH: TDA9952 standby) blanking control input clamp pulse input at optical black preset sample-and-hold pulse input data sample-and-hold pulse input data clock input clamp pulse input at dummy pixel
handbook, full pagewidth
VCCA1 AGND1 AGND2 IN AGND3 AGND4 VCCA2 CPCDS1 CPCDS2
1 2 3 4 5 6
37 OGND2
48 CLPDM
38 VCCO2
40 AGND6
44 CLPOB
41 VCCA6
42 STDBY
46 SHD
45 SHP
47 CLK
43 BLK
39 OE
36 D9 35 D8 34 D7 33 D6 32 D5 31 D4
TDA9952HL
7 8 9 30 D3 29 D2 28 D1 27 D0 26 n.c. 25 n.c.
DCLPC 10 OFDOUT 11 TEST 12
AGND5 13
VCCA3 14
VCCA4 15
VCCA5 16
SDATA 17
SCLK 18
SEN 19
VSYNC 20
VCCD1 21
DGND1 22
VCCO1 23
OGND1 24
FCE483
Note: the HVQFN package pin configuration is identical.
Fig.2 Pin configuration.
2002 Aug 21
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Philips Semiconductors
Preliminary specification
10-bit, 3.0 V, 25 Msps analog-to-digital interface for CCD cameras
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL VCCA VCCD VCCO VCC PARAMETER analog supply voltage digital supply voltage digital outputs supply voltage supply voltage difference between VCCA and VCCD between VCCA and VCCO between VCCD and VCCO Vi Io Tstg Tamb Tj Note 1. All supplies are connected together. HANDLING input voltage data output current storage temperature ambient temperature junction temperature referenced to AGND -0.5 -0.5 -0.5 -0.3 - -55 -20 - +0.5 +1.2 +1.2 +6.5 10 CONDITIONS note 1 note 1 note 1 MIN. -0.3 -0.3 -0.3
TDA9952
MAX. +4.5 +4.5 +4.5 V V V V V V V
UNIT
mA C C C
+150 +75 150
Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling integrated circuits. THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER thermal resistance from junction to ambient CONDITIONS in free air VALUE 76 UNIT K/W
2002 Aug 21
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Philips Semiconductors
Preliminary specification
10-bit, 3.0 V, 25 Msps analog-to-digital interface for CCD cameras
CHARACTERISTICS VCCA = VCCD = 3.0 V; VCCO = 2.5 V; fpix = 25 MHz; Tamb = -20 to +75 C; unless otherwise specified. SYMBOL Supplies VCCA VCCD VCCO ICCA ICCD ICCO analog supply voltage digital supply voltage digital outputs supply voltage analog supply current digital supply current digital outputs supply current total power consumption CL = 10 pF on all data outputs; input ramp of 800 s duration VCCA = VCCD = 3 V; VCCO = 2.5 V VCCA = VCCD = 2.7 V; VCCO = 2.2 V standby mode Digital inputs PINS SHP, SHD AND CLK (REFERENCED TO DGND) VIL VIH Ii Ci VIL VIH Ii Clamps GLOBAL CHARACTERISTICS OF THE CLAMP LOOPS tW(clamp) clamp active pulse width in PGA code = 383 for number of pixels maximum 6 LSB error for a CPCDS capacitance of 1 F; clamp code = 32 CDS input clamp transconductance 15 - - LOW-level input voltage HIGH-level input voltage input current input capacitance 0 Vi 5.5 V 0 2.0 -3 - 0 2.0 0 Vi 5.5 V -2 - - - - - - - all clamps active 2.7 2.7 2.2 - - - 3.0 3.0 2.5 43 2.0 0.5 PARAMETER CONDITIONS MIN. TYP.
TDA9952
MAX.
UNIT
3.6 3.6 3.6 - - -
V V V mA mA mA
Ptot
- - -
135 115 4.5
- - -
mW mW mW
0.8 5.5 +3 2
V V A pF
PINS CLPDM, CLPOB, SEN, SCLK, SDATA STBY, OE, BLK AND VSYNC LOW-level input voltage HIGH-level input voltage input current 0.8 5.5 +2 V V A
pixels
INPUT CLAMP (DRIVEN BY CLPDM) gm(CDS) - 15 - mS
2002 Aug 21
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Philips Semiconductors
Preliminary specification
10-bit, 3.0 V, 25 Msps analog-to-digital interface for CCD cameras
SYMBOL PARAMETER CONDITIONS MIN. - - - - 2 - TYP.
TDA9952
MAX. - - 1.5 3 - -
UNIT
Correlated Double Sampling (CDS) Vi(CDS)(p-p) maximum CDS input voltage (peak-to-peak value) maximum CDS input reset pulse input current into pin IN input capacitance CDS control pulses minimum active time Vi(CDS)(p-p) = 800 mV; black-to-white transition in 1 pixel with 98.5% Vi recovery Figs 3 and 4 at floating gate level VCC = 2.85 V VCC 3.0 V 650 800 - - - 11 mV mV V A pF ns
Vreset(max) Ii(IN) Ci tCDS(min)
th(IN;SHP)
CDS input hold time (pin IN) compared to control pulse SHP CDS input hold time (pin IN) compared to control pulse SHD
3
-
-
ns
th(IN;SHD)
Figs 3 and 4
3
-
-
ns
Programmable Gain Amplifier (PGA) DRPGA GPGA ADC DNL ADCres fpix(max) fpix(min) OCCD(max) differential non linearity ADC resolution ramp input - - 25 OCCD(max) = 100 mV OCCD(max) = 200 mV maximum offset voltage between CCD floating level and CCD dark pixel level CLK pulse width HIGH CLK pulse width LOW time delay between SHD and CLK set-up time of BLK compared to SHD video input voltage for ADC full-scale output Figs 3 and 4 Figs 3 and 4 PGA code = 00 PGA code = 383 - - -200 0.5 10 - - - - 0.9 - - 1 2 +200 LSB bits PGA dynamic range PGA gain step - 0.08 36 0.10 - 0.12 dB dB
Total chain characteristics (CDS + PGA + ADC) maximum pixel rate minimum pixel rate MHz MHz MHz mV
tCLKH tCLKL td(SHD;CLK) tsu(BLK;SHD) Vi(IN)
15 15 - 5 - -
- - 10 - 800 12.7
- - - - - -
ns ns ns ns mV mV
2002 Aug 21
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Philips Semiconductors
Preliminary specification
10-bit, 3.0 V, 25 Msps analog-to-digital interface for CCD cameras
SYMBOL Ntot(rms) PARAMETER CONDITIONS - - - - - - - - - static IOH = -1 mA IOL = 1 mA 0.5 V < Vo < VCCO - VCCO - 0.5 0 -20 5 VCCO = 3.6 V; VCCD = 3.6 V - VCCO = 2.5 V; VCCD = 3.0 V - VCCO = 2.2 V; VCCD = 2.7 V - CL fSCLK(max) Note 1. Noise figure includes the internal input buffer circuit. output load capacitance - 10 Serial interface maximum clock frequency of serial interface - - MIN. 0.4 0.6 145 170 TYP.
TDA9952
MAX. - - - - - -
UNIT LSB LSB V V V V V ppm/K A
total noise from CDS input Fig.8; note 1 to ADC output PGA code = 00 (RMS value) PGA code = 96 equivalent input noise voltage (RMS value) PGA code = 383 PGA code = 96
Ein(rms)
Digital-to-Analog Converter (OFD DAC) VOFDOUT(p-p) output voltage (peak-to-peak value) VOFDOUT(0) DC output voltage for code 0 RL = 1 M Fig.5 Fig.5 1.0 VAGND
VOFDOUT(255) DC output voltage for code 255 TCDAC ZOFDOUT IOFDOUT DAC output temperature coefficient DAC output impedance DAC output current drive
VAGND + 1.0 - 250 2000 - - - - - 10 12 13 - - - 100
Digital outputs fpix = 25 MHz; CL = 10 pF; see Figs 3 and 4 VOH VOL IOZ th(o) td(o) HIGH-level output voltage LOW-level output voltage output current in 3-state mode output hold time output delay time VCCO 0.5 +20 - 13 15 16 20 V V A ns ns ns ns pF
MHz
2002 Aug 21
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IN N N+1 tCDS(min) 2.0 V SHP 0.8 V th(IN;SHP) N+2 N+3 N+4 N+5 tCDS(min) 2.0 V SHD 0.8 V th(IN;SHD) tCLKH 0.8 V 2.0 V
handbook, full pagewidth
Philips Semiconductors
10-bit, 3.0 V, 25 Msps analog-to-digital interface for CCD cameras
11
CLK DATA BLK
2.0 V 0.8 V td(SHD;CLK)
2.0 V 0.8 V
N-4
N-3
50%
N-2
N-1
N
ADC CLAMP CODE
th(o) td(o) 2.0 V
MGU673
Preliminary specification
tsu(BLK;SHD)
TDA9952
SHP and SHD should be aligned at optimum with the CCD signal. Samples are taken at falling edge. Recommended placement for CLK rising edge is between the falling edge of SHD and the rising edge of SHP.
Fig.3 Pixel frequency timing diagram; all polarities active HIGH.
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IN N N+1 N+2 N+3 N+4 N+5 2.0 V SHP 0.8 V th(IN;SHP) 2.0 V SHD 0.8 V th(IN;SHD) tCDS(min) tCDS(min) 2.0 V 0.8 V
handbook, full pagewidth
Philips Semiconductors
10-bit, 3.0 V, 25 Msps analog-to-digital interface for CCD cameras
12
CLK 0.8 V tCLKL DATA N-4 BLK
2.0 V
2.0 V 0.8 V td(SHD;CLK) ADC CLAMP CODE
N-3
50%
N-2
N-1
N
th(o) td(o)
0.8 V
Preliminary specification
MGU672
tsu(BLK;SHD)
TDA9952
SHP and SHD should be aligned at optimum with the CCD signal. Samples are taken at rising edge. Recommended placement for CLK falling edge is between the rising edge of SHD and the falling edge of SHP.
Fig.4 Pixel frequency timing diagram; all polarities active LOW.
Philips Semiconductors
Preliminary specification
10-bit, 3.0 V, 25 Msps analog-to-digital interface for CCD cameras
TDA9952
handbook, halfpage
FCE486
1.0 OFDOUT DAC voltage output (V)
0 0 OFDOUT control DAC input code 255
Fig.5 DAC voltage output as a function of DAC input code.
handbook, full pagewidth
CLPOB WINDOW VIDEO OPTICAL BLACK HORIZONTAL FLYBACK
CLPDM WINDOW DUMMY VIDEO
D[9:0] (digital outputs)
CLPOB (active HIGH)
CLPDM (active HIGH)
BLK (active HIGH) BLK window
FCE487
Fig.6 Line frequency timing diagram.
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Philips Semiconductors
Preliminary specification
10-bit, 3.0 V, 25 Msps analog-to-digital interface for CCD cameras
TDA9952
handbook, halfpage
37.9
42 TOTAL gain (dB) 36 30 24 18 12 6
MGU671
1.9
0 0 64 128 192 256 320 384 448 511 PGA input code
PGAcode Gain ( dB ) = 1.9 + 36 x --------------------------- [ dB ] - 383 Full-scale at the ADC input is reached at Vi(CDS)(p-p) = 800 mV; PGA code 0.
Fig.7 Total gain from CDS input to ADC input as a function of PGA control code.
handbook, halfpage N
14 tot(rms) (LSB) 12 10 8 6 4 2 0
FCE489
0
64
128
192
256
320
383
PGA code
Noise measurement at ADC outputs: Coupling capacitor at input is grounded, so only noise contribution of the front-end is evaluated. Front-end works at 25 Mpixels with line of 1024 pixels whose first 40 are used to run CLPOB and the last 40 for CLPDM. Data at the ADC outputs are measured during the other pixels. As a result of this, the standard deviation of the codes statistic is computed, resulting in the noise. No quantization noise is taken into account because there is no input.
Fig.8 Typical total noise performance as a function of PGA gain.
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Philips Semiconductors
Preliminary specification
10-bit, 3.0 V, 25 Msps analog-to-digital interface for CCD cameras
SERIAL INTERFACE
TDA9952
SDATA handbook, full pagewidth SD0 SCLK LSB 12 SEN SD1 SD2 SD3 SD4
SHIFT REGISTER SD5 SD6 SD7 SD8 SD9 SD10 SD11 A0 MSB LATCH SELECTION A1 A2 A3
8 OFDOUT DAC LATCHES
9 PGA GAIN LATCHES
6 ADC CLAMP LATCHES
10 CONTROL PULSE POLARITY LATCHES CONDITIONING VSYNC VSYNC
LOAD FLIP-FLOP FLIP-FLOP FLIP-FLOP
8-bit DAC
PGA control
ADC clamp control
control pulses polarity settings
FCE490
First logical layer (DFF) is clocked by first falling SCLK edge after rising SEN edge. Second logical layer is clocked by LOAD signal; this signal depends on VSYNC signal. If vertical sync signal is not available, VSYNC should be connected to SEN.
Fig.9 Serial interface block diagram.
2002 Aug 21
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Philips Semiconductors
Preliminary specification
10-bit, 3.0 V, 25 Msps analog-to-digital interface for CCD cameras
TDA9952
handbook, full pagewidth
tsu2 MSB thd4 SD9 SD8 SD7 SD6 SD5 SD4 SD3 SD2 SD1 LSB SD0
SDATA
A3
A2
A1
A0
SD11 SD10
SCLK
SEN tsu1 tsu3 thd5 thd6
FCE491
VSYNC
tsu1 = tsu2 = tsu3 = 10 ns (minimum); thd4 = thd5 = thd6 = 10 ns (minimum).
Fig.10 Loading sequence of control input data via the serial interface.
2002 Aug 21
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Philips Semiconductors
Preliminary specification
10-bit, 3.0 V, 25 Msps analog-to-digital interface for CCD cameras
Table 1 Serial interface programming ADDRESS BITS DATA BITS SD11 TO SD0 A3 0 0 0 0 A2 0 0 0 0 A1 0 0 1 1 A0 0 1 0 1 PGA gain control (SD8 to SD0) DAC OFDOUT output control (SD7 to SD0) ADC clamp reference control (SD5 to SD0); from code 0 to 63
TDA9952
control pulses (pins SHP, SHD, CLPDM, CLPOB, BLK and CLK) polarity settings; SD2, SD6, SD7 and SD9 should be set to logic 1; for SD6 and SD7 see Tables 3 and 4 test modes (not to be used in normal applications)
other addresses Table 2 Polarity settings PIN SHP and SHD CLK CLPDM CLPOB BLK VSYNC Table 3
DATA BIT SD4 SD5 SD0 SD1 SD3 SD8
ACTIVE EDGE OR LEVEL 1 = HIGH; 0 = LOW 1 = rising; 0 = falling 1 = HIGH; 0 = LOW 1 = HIGH; 0 = LOW 1 = HIGH; 0 = LOW 0 = rising; 1 = falling
Standby control using pin STDBY or serial interface DATA BIT SD7 1 0 PIN STDBY HIGH LOW HIGH LOW ICCA + ICCD (typical) 1.5 mA 45 mA 45 mA 1.5 mA
Table 4
Output enable selection using output enable pin OE or serial interface) DATA BIT SD6 1 0 PIN OE LOW HIGH LOW HIGH ADC DIGITAL OUTPUTS D9 TO D0 active binary high-impedance high-impedance active binary
When power supplies increase from zero, an init-on-power block initializes the circuit as follows: * PGA gain code is set to 000 * Clamp code is set to 00 * All polarity settings are set to logic 1 * Input OFD is set to logic 0.
2002 Aug 21
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Philips Semiconductors
Preliminary specification
10-bit, 3.0 V, 25 Msps analog-to-digital interface for CCD cameras
APPLICATION INFORMATION
TDA9952
handbook, full pagewidth
VCCD
VCCD
VCCA
VCCO
100 nF
(2) (2)
100 nF
AGND6
CLPOB
1 F VCCA 100 nF VCCA1 AGND1 AGND2 IN AGND3 AGND4 VCCA 100 nF 1 F 1 F VCCA2 CPCDS1 CPCDS2 DCPLC 1 F OFDOUT TEST
48 47 46 45 44 43 42 41 40 39 38 37 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 36 35 34 33 32 31 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
TDA9952
30 29 28 27 26 25
OGND2
CLPDM
STDBY
SHP
VCCA6
SHD
CLK
VCCO2
CCD(1)(2)
BLK
OE
n.c n.c
VCCO1
100 nF VCCA
serial interface
(3)
100 nF VCCD
100 nF
FCE757
VCCO
(1) As an internal input buffer is incorporated, depending on the CCD output impedance, an external input buffer may not be necessary and consequently power savings can be made. (2) Input signals IN, SHD and SHP must be adjusted to comply with timing signals th(IN; SHP) and th(IN; SHD) (see Chapter "Characteristics"). (3) Pins SEN and VSYNC should be connected together when the vertical sync signal is not available.
Fig.11 Application diagram.
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OGND1
AGND5
VSYNC
VCCA4
VCCA3
VCCA5
DGND1
SDATA
VCCD1
SCLK
SEN
Philips Semiconductors
Preliminary specification
10-bit, 3.0 V, 25 Msps analog-to-digital interface for CCD cameras
TDA9952
handbook, full pagewidth
(1)
CCD
10-bit data bus
TDA9952
DIGITAL SIGNAL PROCESSOR
MGU674
clamp signals
clock signals
HORIZONTAL AND VERTICAL DRIVER
PULSE PATTERN GENERATOR
(1) The external input buffer can be omitted for CCDs with low output impedance; for CCDs with high output impedance, a small current (around 1 mA) is needed.
Fig.12 Typical imaging application.
Power and grounding recommendations Care should be taken to minimize the noise when designing a printed-circuit board for applications such as PC cameras, surveillance cameras, camcorders and digital still cameras. For the front-end integrated circuit, the basic rules of printed-circuit board design and implementation of analog components (such as classical operational amplifiers) must be taken into account, particularly with respect to power and ground connections. The connections between the CCD interface and the CDS input should be as short as possible and a ground ring protection around these connections can be beneficial. Separate analog and digital supplies provide the best performance. If it is not possible to do this on the board then the analog supply pins must be decoupled effectively from the digital supply pins. The decoupling capacitors must be placed as close as possible to the IC package.
In a two-ground system, in order to minimize the noise through the package and die parasitics, the following recommendation must be implemented: * The ground pin associated with the digital outputs must be connected to the digital ground plane and special care should be taken to avoid feedthrough in the analog ground plane. The analog and digital ground planes must be connected together with an inductor as closely as possible to the IC in order for them to have the same DC voltage. * The digital output pins and their associated lines should be shielded by the digital ground plane which can then be used as a return path for digital signals.
2002 Aug 21
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Philips Semiconductors
Preliminary specification
10-bit, 3.0 V, 25 Msps analog-to-digital interface for CCD cameras
PACKAGE OUTLINES LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm
TDA9952
SOT313-2
c
y X
36 37
25 24 ZE
A
e
E HE
A A2
A1
(A 3) Lp L detail X
wM pin 1 index 48 1 12 ZD bp D HD wM B vM B vM A 13 bp
e
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT313-2 REFERENCES IEC 136E05 JEDEC MS-026 EIAJ EUROPEAN PROJECTION A max. 1.60 A1 0.20 0.05 A2 1.45 1.35 A3 0.25 bp 0.27 0.17 c 0.18 0.12 D (1) 7.1 6.9 E (1) 7.1 6.9 e 0.5 HD 9.15 8.85 HE 9.15 8.85 L 1.0 Lp 0.75 0.45 v 0.2 w 0.12 y 0.1 Z D (1) Z E (1) 0.95 0.55 0.95 0.55 7 0o
o
ISSUE DATE 99-12-27 00-01-19
2002 Aug 21
20
Philips Semiconductors
Preliminary specification
10-bit, 3.0 V, 25 Msps analog-to-digital interface for CCD cameras
TDA9952
HVQFN48: plastic, heatsink very thin quad flat package; no leads; 48 terminals; body 7 x 7 x 0.85 mm
SOT619-1
D
B
A
terminal 1 index area A E A4
detail X
e1 e 13 L 12 25 e
1/2 e
C b 24
v M C A B w M C
y1 C
y
Eh
1/2 e
e2
pin 1 index
1 48 Dh 0 DIMENSIONS (mm are the original dimensions) A UNIT max. mm Note 1.00 A4 max. 0.80 b 0.35 0.18 D (1) 7.05 6.95 Dh 5.25 4.95 E (1) 7.05 6.95 Eh 5.25 4.95 e 0.5 37
36
X 2.5 scale e1 5.5 e2 5.5 L 0.50 0.30 v 0.2 w 0.1 y 0.05 y1 0.1 5 mm
1. Plastic or metal protrusions of 0.076 mm maximum per side are not included. OUTLINE VERSION SOT619-1 REFERENCES IEC JEDEC MO-220 EIAJ EUROPEAN PROJECTION ISSUE DATE 01-06-07 01-08-08
2002 Aug 21
21
Philips Semiconductors
Preliminary specification
10-bit, 3.0 V, 25 Msps analog-to-digital interface for CCD cameras
SOLDERING Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 220 C for thick/large packages, and below 235 C for small/thin packages. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed.
TDA9952
If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
2002 Aug 21
22
Philips Semiconductors
Preliminary specification
10-bit, 3.0 V, 25 Msps analog-to-digital interface for CCD cameras
Suitability of surface mount IC packages for wave and reflow soldering methods PACKAGE(1) BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC(4), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes not suitable not suitable(3)
TDA9952
SOLDERING METHOD WAVE REFLOW(2) suitable suitable suitable suitable suitable
suitable not not recommended(4)(5) recommended(6)
1. For more detailed information on the BGA packages refer to the "(LF)BGA Application Note" (AN01026); order a copy from your Philips Semiconductors sales office. 2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 4. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 6. Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
2002 Aug 21
23
Philips Semiconductors
Preliminary specification
10-bit, 3.0 V, 25 Msps analog-to-digital interface for CCD cameras
DATA SHEET STATUS DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2) Development DEFINITIONS
TDA9952
This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A.
Preliminary data
Qualification
Product data
Production
Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
2002 Aug 21
24
Philips Semiconductors
Preliminary specification
10-bit, 3.0 V, 25 Msps analog-to-digital interface for CCD cameras
NOTES
TDA9952
2002 Aug 21
25
Philips Semiconductors
Preliminary specification
10-bit, 3.0 V, 25 Msps analog-to-digital interface for CCD cameras
NOTES
TDA9952
2002 Aug 21
26
Philips Semiconductors
Preliminary specification
10-bit, 3.0 V, 25 Msps analog-to-digital interface for CCD cameras
NOTES
TDA9952
2002 Aug 21
27
Philips Semiconductors - a worldwide company
Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
(c) Koninklijke Philips Electronics N.V. 2002
SCA74
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
753504/04/pp28
Date of release: 2002
Aug 21
Document order number:
9397 750 09672

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